Semiconductor devices are used in a variety of applications and technologies. Integrated circuits comprised of semiconductor devices are important components of many electronic and mechanical devices and systems, as examples. As semiconductor technology has progressed, the trend has been towards scaling down the size of semiconductor devices, in order to meet market demands for increased speed and performance, and smaller size.
A recent development in the semiconductor industry is the use of silicon nanocrystals. Silicon nanocrystals comprise very small silicon structures that may comprise a diameter of a few nanometers, e.g., ranging from about 2 to 10 nm. Because of their small size, they exhibit electrical, optical, and other properties that are advantageous in certain applications. Silicon nanocrystals are predicted to be useful in semiconductor applications such as non-volatile memory devices, optics, and other types of semiconductor devices.
One type of semiconductor device is a memory device, which is used to store information, typically as a logic “1” or “0”. Memory devices may be static or dynamic. More recent memory designs comprise non-volatile memory (NVM) devices, which do not require that the data be refreshed during normal operation, as in dynamic memory devices, for example, and the data survives even with the power supply cut off, in contrast with static memory devices. Flash memory, used in digital cameras, for example, is one type of NVM device. Flash memory cells store a charge in a floating gate and are ‘programmed’ e.g., using Fowler-Nordheim tunneling, although flash memory cells may alternatively be programmed using other methods, such as channel hot electron injection.
Because current designs of flash memory cells are already quite small, it is a challenge to further shrink their size, due to the risk of losing data retention, degrading reliability, increasing floating gate interference, and drain turn on effect, as examples. Further reducing the size is particularly challenging for embedded flash memory cells, which comprise flash memory cells formed on the same integrated circuit or die as support circuitry and components, such as high voltage, peripheral, and logic circuitry. One proposed concept to reduce the size of flash memory cells is the use of discrete silicon nanocrystals instead of a polysilicon floating gate: the continuous floating gate is replaced by a plurality of nanocrystalline islands.
Some proposed integration schemes for implementation of silicon nanocrystals in flash memory cells involve depositing a blanket layer of silicon nanocrystals over an entire surface of a workpiece, and removing the deposited layer of silicon nanocrystals in areas where the silicon nanocrystals are not needed, as shown in FIGS. 1 and 2 in a cross-sectional view. The silicon nanocrystals are usually embedded in silicon dioxide or other insulating materials, for example. Proposed methods of forming silicon nanocrystals include one-step and two-step processes, with and without pre-treatment of the surface, as examples. The use of silicon nanocrystals instead of a floating gate has been found to decrease the operating and programming voltages of flash memory cells, which is advantageous, because the power requirements for the flash memory cells are decreased, and the periphery circuitry can be reduced in size.
However, the etch process for the removal of the silicon nanocrystals in undesired areas of a semiconductor device, such as in the regions for support circuitry and over the source and drain regions of the flash memory cell, is challenging, because the silicon and silicon dioxide of the layer of silicon nanocrystals must be removed selectively to silicon and silicon dioxide material layers already present in underlying material layers of the device. These etch processes require additional lithography steps and masking techniques, and may comprise etch processes that do not utilize an etch stop layer. Rather, the etch processes are stopped after a predetermined period of time; thus, the etch processes are poorly reproducible. Furthermore, damage to the top surface of the substrate and various material layers can occur during the etch processes, resulting in unpredictable or decreased device performance, and device failures. Another problem with attempting to etch away the undesired silicon nanocrystals is that the silicon nanocrystals and the insulating material the silicon nanocrystals are embedded in may not be etched away completely, also causing decreased device performance and device failures.
Another proposed integration scheme is to form silicon nanocrystals by implantation and a subsequent anneal, which lends itself to a patterned deposition when an implantation mask is employed. However, for flash memory devices, the end-of-range damage created by the implantation process has been found to be quite detrimental to the data retention properties of the flash memory cells.
Another proposed integration scheme for forming silicon nanocrystals is a lift-off technique, wherein a layer of silicon nanocrystals is removed together with a mask that is situated underneath the silicon nanocrystal layer. However, selecting a lift-off process that will not attack the nanocrystals or the substrate in the areas where they are supposed to remain is difficult, and the masking material has to be relatively thick for the lift-off to work correctly. An additional complication is that the nanocrystals will not be able to be embedded before the lift-off without impacting the ability to lift-off the mask fully. Furthermore, the nanocrystals on the mask tend to become loose during the lift-off process, and it is difficult to keep the nanocrystals in suspension. This results in an inability to create a production-worthy process, or in an inability to use a very fine pattern, as is required to integrate a substantial amount of flash memory cells.
Thus, what are needed in the art are improved methods of forming silicon nanocrystals and other types of nanocrystals in semiconductor devices.